Fast Multiplication Energy - Efficient 7 : 2 Compressor

In many of digital systems used in like graphical processors, digital signal processors fast parallel multiplication using adder trees are present. Multipliers have attracted lots of researchers’ attention into making high-performance multipliers to consume less power and operate faster. This paper presents efficient implementation of comp ress tree adders on FPGAs. A new 7:2 compr essor architecture based on changing some internal equations are proposed. In addition, using an effi cient full-adder (FA) block is considered to have a high speed compressor. Three 7:2 compresso rs are considered for comparison. The proposed architecture is compared with the best existing designs presented in the state-of-the-art literature in terms of power, delay and area. The paper presents 7:2 compressors that are widely used as building blocks of multipliers. Lots of architectures for 5:2 compressors have been proposed in the literature. The number of transistors used in the design is less than the best existing 5:2 compr essor architectures. By a vast research on these structures, it has been revealed that the structures presented in and have better performance than